1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory, and more particularly to a non-volatile semiconductor memory in which an impurity concentration of a source region is set low to make the source region smaller in size, thereby achieving a more highly integrated device and performing writing operation by an FN tunnel current.
2. Description of the Related Art
Conventionally, a flash memory having a floating gate has been used as a non-volatile semiconductor memory. The layout, structure and operation of the flash memory will be described below with reference to FIGS. 14 to 18.
FIG. 14 is a plan view showing a layout of a flash memory according to the prior art. In a layout of the flash memory where a plurality of memory cells are arranged in a matrix as shown in FIG. 14, 201 denotes a metal wiring for connecting drains of memory cells in common to form a bit line BL, 202 denotes a control gate region for connecting control gates of memory cells in common to form a word line WL, 203 denotes a floating gate region, and 204 denotes a contact for supplying an operating voltage from the metal wiring 201 to each drain.
FIG. 15 is a sectional view showing the flash memory according to the prior art, which is taken along the line a-a' in FIG. 14. FIG. 16 is a sectional view showing the flash memory according to the prior art, which is taken along the line b-b' in FIG. 14. FIG. 17 is a sectional view showing the flash memory according to the prior art, which is taken along the line c-c' in FIG. 14.
An example of a structure of the flash memory according to the prior art will be described below with reference to FIGS. 15 to 17.
As an example of the structure of the flash memory according to the prior art, a memory cell is formed on a P type silicon substrate 205 and an active region 206 is defined on the surface of the silicon substrate 205 by forming a device isolation region 207 (LOCOS oxide film) using a LOCOS (Local Oxidation of Silicon) method (FIG. 16). A channel region 208, a source region (an N+ diffusion layer) 209 and a drain region (N+ diffusion layer) 210 are formed in the active region 206. The channel region 208 is formed between the source region 209 and the drain region 210 (FIG. 15). A contact hole 204a is formed on the drain region 210. The contact hole 204a is filled with a tungsten plug on which the metal wiring 201 serving as the bit line BL is provided (FIG. 15).
A tunnel oxide film 211 is formed on the active region 206. Furthermore, a floating gate 203 comprising an N+polysilicon (Poly Si) layer is formed to cover the tunnel oxide film 211 and a part of the device isolation region 207 (FIG. 16). The floating gate 203 is covered with a three-layered film comprising an oxide film, a nitride film and an oxide film on which a control gate 202 comprising a tungsten polycide (WSi-Poly Si) is formed vertically in self-alignment with the floating gate 203 (FIG. 16). The control gate 202 forms the word line WL perpendicular to the metal wiring 201.
On a side in a space between the control gates where the source region 209 is formed, the LOCOS oxide film is removed and a common source line 212 composed of a N+diffusion layer and arranged in parallel with the word line WL is formed. Furthermore, an interlayer dielectric film 213 is formed on the common source line 212 (FIG. 17).
FIG. 18 is a diagram showing an equivalent curcuit and an operating voltage during operation of the flash memory according to the prior art. In FIG. 18, a plurality of memory cells Q are arranged in a matrix, a plurality of bit lines BL connected to drains d of the memory cells Q are wired longitudinally, a plurality of word lines WL connected to control gates g of the memory cells are wired laterally, and a plurality of common source lines SL connected to sources s of the memory cells are wired in parallel with the word lines WL.
The operaion voltage in performing writing, erasing and reading of the flash memory according to the prior art is as follows. The writing operation is performed by applying a voltage of 5 V to a selected bit line BL, a voltage of 12 V to a selected word line WL, and a voltage 0 V to a source line SL and a substrate SB to inject hot electrons into the floating gate 203. The erasing operation is performed by applying a voltage of 5 V to a source line SL, -10 V to a word line WL and 0 V to a substrate SB, and making the bit line BL open to extract the electrons from the floating gate 203 to the source line SL by an FN (Fowler-Nordheim) tunnel current. The reading operation is performed by applying a voltage of 1 V to a selected bit line BL, 5 V to a selected word line WL and 0 V to a substrate SB and determining whether or not a current flows to the source of the selected memory cell.
In the flash memory according to the prior art, however, an efficiency of generation of the hot electrons should be maintained during the writing operation, the FN tunnel current should be prevented from being lowered during the erasing operation, and high-speed random access operation should be maintained during the reading operation. For this reason, it is necessary to reduce a resistance value of the diffusion layer of the common source line in respect of the structure of the flash memory according to the prior art, for example. Consequently, a dosage of impurities implanted into the diffusion layer of the common source line should be increased.
As a well-known example in which a source resistance value of the diffusion layer of the common source line is reduced, Japanese Unexamined Patent Publication No. SHO 61(1986)-30063 has proposed a non-volatile semiconductor memory in which N type impurities are implanted with high dosage into a common source line region and a refractory metal silicide is then formed on a surface of the common source line region in self-alignment.
According to the non-volatile semiconductor memory disclosed in the Japanese Unexamined Patent Publication No. SHO 61(1986)-30063, the resistance is reduced by using a silicide so as to fully perform the writing operation by hot electrons. However, there are the following problems.
1. Since electrons are extracted toward a source during erasing operation, impurity concentration of the source region cannot be reduced, so that the length of the source region cannot be reduced (the channel length cannot be reduced). PA1 2. Since arsenic exists at a high concentration in the source, the resistance of the silicide is increased when the source region is reduced.